1. Field of the Invention
The present invention relates generally to a spread spectrum receiver. More specifically, the invention relates to a fading period detecting system for a synchronization acquisition and a transmission power control.
2. Description of the Related Art
In a multiple access system for mutual communication between a plurality of stations utilizing assigned frequency band, there has been proposed various communication systems, such as a frequency division multiple access (FDMA) system, a time division multiple access (TDMA) system, code division multiple access (CDMA) system and so forth. In most of these systems, a base station is arranged in each of cells which is established by dividing a service area into small areas, and a subscriber terminal communicates with another subscriber terminal via the base station.
Amongst, the CDMA system which does not require burst synchronization, is suitable for a communication system having a large number of subscribers and is strong against interference and jamming. Therefore, the CDMA system has been attracting attention. The CDMA system employing a spread spectrum communication system is a multiple access system assigning mutually distinct spreading code series for respective users and performing spread modulation utilizing the same. Accordingly, even in one cell, the same frequency can be used by a plurality of users.
As is well known, the spread spectrum communication system is premised to use a spreading code synchronized with the spreading code used at the transmission side in demodulation by despreading of a reception signal. For example, when the diffusion signal is shifted over one chip due to influence of variation of propagation path delay or so forth due to multiple path or so forth, it becomes difficult to accurately demodulate data. Therefore, a technology for synchronization acquisition (initial synchronization) for reducing a phase difference of transmission side and reception side spreading code series (normally, less than or equal to half chip) and synchronization tracking (synchronization holding) for maintaining a necessary chip accuracy so as not to lose track of the once acquisited synchronization position due to influence of noise or demodulation, are indispensable.
Conventionally, this kind of synchronization acquisition circuit is employed for the purpose of acquisition of chip phase synchronization of the spreading code in the spread spectrum receiver, as disclosed in Japanese Unexamined Patent Publication No. Heisei 7-202843, for example.
FIG. 11 is a block diagram showing one example of the conventional spread spectrum receiver and its synchronization acquisition circuit. As shown in FIG. 11, the conventional spread spectrum receiver has an orthogonal demodulator 11 connected to a reception antenna 10, an A/D converter 12 for performing analog-to-digital conversion of an output of the orthogonal demodulator 11, a RAKE demodulator 30 connected to an output of the A/D converter 12, a synchronization acquisition tracking unit 40 similarly connected to the output of the A/D converter 12 and a decoder 14 connected to the output of the RAKE demodulator 30.
The RAKE demodulator 30 performs maximum ratio synthesis of upper three outputs in the order of electric power among correlated demodulation output. Each correlated demodulation output by each of three demodulation circuits 31-1 to 31-3 which perform correlated demodulation on the basis of phase information obtained from the synchronization acquisition tracking unit, is output with synthesis by a RAKE synthesizing circuit 32.
In the synchronization acquisition tracking unit 40, a correlated power is calculated by a correlator 41. The correlated power is integrated by an integrator 42. An integrated output of the integrator 42 is sequentially switched by a switch 43 at a period Tr (about Tw/100) which is sufficiently shorter than a Rayleigh fading period Tw (about several Hz to 100 Hz). The correlated power integrated by each of these periods are integrated by inputting to N in number of integrators 44-1 to 44-N. Then at a timing where a preliminarily designated fixed integration period is reached, a switch 45 is switched for outputting phase shifting amounts corresponding to integrators among the integrators 44-1 to 44-N outputting largest three integrated values. In a manner set forth above, synchronization acquisition is performed.
A problem encountered in the prior art set forth above is that the predeterminarily designated and fixed integration period does not match with an actual fading period. If the set fixed integration period is short, when the fading period is long, it is possible to perform integration for a falling down portion of fading. On the other hand, if the set integration period is long, when the fading period is short, integration can be performed for unnecessarily long period to slow-down follow-up of the path and whereby to cause degradation of synchronization acquisition ability.
The reason is that since the fading frequency is sequentially varied depending upon moving speed of a mobile terminal, an integration period of an optimal correlated value cannot be obtained.